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AD1928
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Rev. 0 | Page 9 of 32
A
48
L
47
A
46
A
45
A
44
A
43
N
42
N
41
N
40
N
39
C
38
A
37
13
14
15
16
17
18
19
20
21
22
23
D
D
D
D
D
D
A
A
A
A
C
C
24
1
2
3
4
5
6
7
8
9
10
11
12
AGND
36
FILTR
35
AGND
34
AVDD
33
AGND
32
OR2
31
OL2
30
OR1
29
OL1
28
CLATCH
27
CCLK
26
DGND
25
AGND
MCLKI/XI
MCLKO/XO
AGND
AVDD
OL3
OR3
OL4
OR4
PD/RST
DSDATA4
DGND
AD1928
TOP VIEW
(Not to Scale)
SINGLE-ENDED
OUTPUT
NC = NO CONNECT
0
Figure 2. Pin Configuration, 48-Lead LQFP
Table 10. Pin Function Descriptions
Pin No.
Input/Output
1
I
2
I
3
O
4
I
5
I
6
O
7
O
8
O
9
O
10
I
11
I/O
12
I
13
I
14
I/O
15
I/O
16
I
17
I/O
18
I/O
19
I/O
20
O
21
I/O
22
I/O
23
I
24
I/O
25
I
26
I
27
I
Mnemonic
AGND
MCLKI/XI
MCLKO/XO
AGND
AVDD
OL3
OR3
OL4
OR4
PD/RST
DSDATA4
DGND
DVDD
DSDATA3
DSDATA2
DSDATA1
DBCLK
DLRCLK
ASDATA1
ADCTDMOUT
ABCLK
ALRCLK
CIN
COUT
DGND
CCLK
CLATCH
Description
Analog Ground.
Master Clock Input/Crystal Oscillator Input.
Master Clock Output/Crystal Oscillator Output.
Analog Ground.
Analog Power Supply. Connect to analog 3.3 V supply.
DAC Left 3 Output.
DAC Right 3Output.
DAC Left 4 Output.
DAC Right 4 Output.
Power-Down Reset (Active Low).
DAC Input 4 (Input to DAC L4 and R4)/DAC TDM Data Output 2/AUX ADC 1 Data Input.
Digital Ground.
Digital Power Supply. Connect to digital 3.3 V supply.
DAC Input 3 (Input to DAC L3 and R3)/DAC TDM Data Input 2/AUX DAC 2 Data Output.
DAC Input 2 (Input to DAC L2 and R2)/DAC TDM Data Output 1/AUX ADC 1 Data Input.
DAC Input 1 (Input to DAC L1 and R1)/DAC TDM Data Input 1/AUX ADC 2 Data Input.
Bit Clock for DACs.
LR Clock for DACs.
ADC Serial Data Output 1 (ADC L1 and R1)/ADC TDM Data Input/AUX DAC 1 Data Output.
ADC TDM Data Output.
Bit Clock for ADCs.
LR Clock for ADCs.
Control Data Input (SPI).
Control Data Output (SPI).
Digital Ground.
Control Clock Input (SPI).
Latch Input for Control Data (SPI).
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